This invention relates, in general, to semiconductor devices and, more particularly, to semiconductor devices having features with sub-photolithographic dimensions.
With an ever increasing demand for smaller and more compact semiconductor devices having higher performance and less power consumption, manufacturers are incorporating designs that require sub-photolithographic features. For example, in metal oxide semiconductor field effect transistor (MOSFET) devices having sub-micron channel lengths, sub-micron features (e.g., doped regions having less than 0.4 micron dimensions) are being incorporated into the channel region between the source and drain regions to improve performance. These doped regions must have precise dimensions in order to fully achieve improved performance. In other words, variations in the dimensions of these features can detrimentally impact device performance.
Conventional lithographic techniques are inadequate to accurately and reproducibly form sub-micron features less than about 0.4 microns. Alternative methods for forming sub-micron features include phase shifting technology, electron beam lithography, ion beam lithography, and x-ray lithography. Although phase shifting technology can provide 0.35 micron features, it is also expensive and complicated. Further, although electron beam lithography, ion beam lithography, and x-ray lithography can provide 0.1 micron features, these techniques are currently non-standard, expensive, and complicated.
As is readily apparent, methods are needed for providing sub-photolithographic features that overcome the disadvantages of the prior art. These methods should be accurate, reproducible, scalable, and cost effective.